1. Field
Exemplary embodiments of the present invention relate to an Image Sensor (IS), and more particularly, to a Double Data Rate (DDR) counter, and an analog-to-digital converter (ADC) and a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor using the DDR counter. The DDR counter may be used for single-slope ADC of a CMOS Image Sensor (CIS) and perform the same analog-to-digital conversion function as a Single Data Rate (SDR) counter at half the clock frequency of the SDR counter.
Although a single-slope ADC is described as an example in the following embodiments, the inventive concept and technology of the present invention are not limited to this, and the technology of the present invention is applicable to multi-slope ADC or other devices employing a DDR counter.
2. Description of the Related Art
Counters are used in many electronic devices to convert physical parameters, such as light intensity, sound intensity and time, into digital signals.
For example, image sensors acquire images using properties of semiconductors that respond to incident light, and include analog-to-digital converters (ADC) that convert analog signals from a pixel array into digital signals. An ADC may be realized using a counter that performs counting operations using a dock. In other words, a single-slope ADC used for a CMOS image sensor uses a counter to convert a pulse signal into a code signal.
The operating speed and power consumption of counters have direct influence on the performance of the devices they operate in. In particular, CMOS image sensors may include counters to convert analog signals, which are outputted on a column basis from an active pixel sensor array, into digital signals. The number of counters may increase depending on the resolution of the CMOS image sensor. As the number of counters increase, the operating speed and power consumption of the counters become an important factor in determining overall performance of the CMOS image sensor.
For this reason, double data rate (DDR) counters have been developed and applied to single-slope ADCs. A DDR counter may reduce its operating speed while maintaining resolution using a single-slope ADC to reduce power consumption.
The DDR counter uses a logic high state and a logic low state of a clock as a Least Significant Bit (LSB) signal.
However, the DDR counter may cause an error of one code or more due to the relationship between the polarity of the input clock and the counting start signal.
Also, the DDR counter may consume more power due to complicated input clock controls, LSB holding controls, signals and so on.